Analytics systems in defence often deal with high volumes of streaming data, applying complex queries to detect sensitive patterns. To support such work alternative hardware architectures have been exploited due to their support for high throughput, low latency computation. Field programmable gate arrays (FPGAs) offer a programmable hardware platform that allows custom architectures for such search operations to be highly efficient. However, the programming paradigms are low level and cumbersome. Hence, alternative approaches based around flexible architectures and custom compilers are required to allow such platforms to be exploited further.
Explaining the science
The NAIL Framework allows multiple hardware accelerators on an FPGA to be integrated within a general computing framework to accelerate a set of workloads that can benefit from parallelisation on FPGA. At present this is proprietary and restricted, with a fixed architecture that can combine a fixed number of static accelerator units, determined in advance, on an FPGA, and a software framework that interacts with this architecture to offer programmers the required interface. NAIL is presently deployed as an accelerator in standard servers.
This project aims to support the broader release of the NAIL Framework, porting to Xilinx devices, support for partial reconfiguration to allow dynamic accelerator loading, and to lay the groundwork for more ambitious evolution, such as to direct-network-attached accelerators. This will allow this framework to find wider use, enable the recruitment of more experienced engineers, and offer the benefits of alternative deployment scenarios and expanded use within the defence community. In addition, this works supports broader aims of exploiting heterogenous architectures to improve performance, efficiency, and flexibility of analytics systems.